1. Field of Invention
The present invention generally relates to a voltage-down device, and more particularly to a digital voltage-down device.
2. Description of Related Art
Low-voltage and low-power integrated circuit design draws greater attention over the past few years as electronic devices become more compact in size and lighter in weight. The reason behind is that the reliability and power dissipation problems that down-sized transistors have encountered. The introduction of portable electronic devices further reveals the importance of low-voltage and low-power devices. Take the complementary metal oxide semiconductor (CMOS) circuits for example. There are three major types of power dissipation involved, among which the dynamic power dissipation P.sub.d is the most important one. The dynamic power dissipation for one charge-discharge cycle is P.sub.d =CV.sub.DD.sup.2 f, in which C is the equivalent loading capacitance, V.sub.DD is the operating voltage, and f is the operating frequency. Apparently, the power dissipation can be reduced if the operating voltage V.sub.DD is reduced. However, the delay time in the circuits nevertheless increases by doing so.
Refer to FIG. 1A, which shows a circuit diagram of a conventional switching-type DC--DC voltage-down converter. An input voltage V.sub.IN is reduced to a lower output voltage V.sub.OUT as the operating voltage to logic gates in the integrated circuits. In FIG. 1, control pulse signals .phi.pp and .phi.nn having different phases are used as inputs to a PMOS transistor 20 and a NMOS transistor 22 so that the PMOS transistor 20 and the NMOS transistor 22 can be alternatively turned on to generate a pulse signal V.sub.x. Subsequently, the pulse signal V.sub.x is filtered by a low-pass filter 24 comprising an inductor L.sub.f and a capacitor C.sub.L to generate a steady-state DC output voltage V.sub.OUT. The input voltage V.sub.IN and output voltage V.sub.OUT have a relationship of V.sub.OUT =D.multidot.V.sub.IN, in which D is the duty cycle defined as D=T.sub.ON /T.sub.CYCLE, T.sub.ON is elapsed time when the pulse signal is at logic "1" state, and T.sub.CYCLE is the period of a pulse signal. For easy reference, several design formulas to design a steady-state DC--DC voltage-down converter are listed below. ##EQU1##
where .DELTA.I.sub.L is the variation of current flowed through the inductor L.sub.f in the low-pass filter 24, .DELTA.V.sub.OUT is the variation of voltage across the capacitor C.sub.L in the low-pass filter 24,f.sub.0 is the operating frequency of the pulse signal, and D is the duty cycle.
From the above formulas, it is understood that a set of control pulse signals .phi. pp and .phi.nn to obtain an accurate duty cycle need to be provided, based on which the inductance L.sub.f and the capacitance C.sub.L in the low-pass filter 24 can be calculated to obtain a desirable steady-state DC output voltage.
Refer to FIG. 1B, which shows a circuit diagram of a conventional pulse-width modulator (PWM) comprising a counter 26, a D flip-flop 28, and a RS flip-flop 30. The PWM generates a pulse signal whose duty cycle is controlled by a duty cycle control signal. Generally, the PWM requires a pulse signal f.sub.high as an input signal to the counter 26, whose frequency is M times as high as the operating frequency of a clocking signal CLK(f.sub.0) so as to generate PWM outputs with different duty cycles. At the initial stage, the PWM output signal from the RS flip-flop 30 in the PWM circuit is set to logic "1" state. When the counter 26 detects a preset period L, the PWM output signal is then reset to logic "0" state so as to generate a pulse signal having a frequency f.sub.0 and a duty cycle L/M. Unfortunately, the PWM circuit requires a control pulse signal with a frequency M times as high as the operating frequency f.sub.0 as an input signal. This will increase power dissipation in the PWM circuit, and consequently reduce the working efficiency of the DC--DC voltage-down converter. Furthermore, when a better accuracy for the output voltage is required, the duty cycle demands a higher accuracy. Thus, the pulse signal f.sub.high with an even higher frequency than the operating frequency f.sub.0 is then inevitably required. For example, when the operating frequency f.sub.0 =1 MHz and 128 adjustment levels for the output voltage are required, the frequency required for the pulse signal f.sub.high will be up to 128 MHz. Therefore, not only the power dissipation significantly increases, but also the complexities in designing the circuits.
Refer to FIG. 1C, which shows a circuit diagram of another conventional pulse-width modulator (PWM), in which a tapped delay line circuit is used to generate a PWM output signal having a desired duty cycle based on a digital control word. The number of the tapped buffers 32 is the same as that of different duty cycles required. When a pulse signal CLK(f.sub.0) is received, the PWM output signal from the RS flip-flop 36 is set to logic "1" state. When the 2.sup.N -to-one multiplexer 38 receives a N-digits duty-cycle control signal, an output signal from one of the tapped buffer is generated at the output terminal of the multiplexer 38 to reset the RS flip-flop 36 so that the PWM output signal is set to logic "0" state. The approach no longer requires a pulse signal f.sub.high which has a frequency M-times as high as the operating frequency f.sub.0. However, it is very difficult to fabricate tapped buffers having an identical delay time T.sub.CELL =1/MT.sub.0. Furthermore, because the delay time of each buffer is fixed, if T.sub.0 (f.sub.0) is changed, the duty cycle generated by this tapped delay line is no longer the desired one.
As a summary, the conventional DC--DC voltage-down converter requires an accurate duty cycle to obtain a steady-state DC output voltage. Furthermore, the PWM circuit requires a pulse signal f.sub.high as an input, which requires a frequency M-times as high as the operating frequency. Therefore, the power dissipation of the PWM circuit increases and the working efficiency of the DC--DC voltage-down converter is reduced.